1. Field of the Invention
The present invention relates to a load drive device for controlling the driving of a load.
2. Description of Related Art
<First Background Art>
FIG. 17 is a view showing a first conventional example of a load drive device. The load drive device 100 shown in FIG. 17 is a semiconductor integrated circuit device provided with an output transistor 101 as switching means for driving a load 200 connected to an output terminal OUT.
A connection detection circuit 400 for detecting whether a load 200 is connected to the load drive device 100 and outputting a detection signal DET to a CPU 300 is formed by a discrete component in a set equipped with the load drive device 100 of prior art.
The connection detection circuit 400 is configured to divide a voltage Va that appears at one end of the load 200 using a resistor 401 and a resistor 402 to generate a divided voltage Vb, and to generate a connection detection signal DET by presenting the divided voltage to a logic gate 403 (a buffer or the like) in order to detect a connection between the load drive device 100 and the load 200, in a state in which an output transistor 101 housed in the load drive device 100 has been switched on.
Specifically, if the load 200 is connected to a semiconductor device 100, the connection detection signal DET is a low level because the voltage Va is brought down to nearly ground potential (GND) via the output transistor 101, which has been switched on. On the other hand, if the load 200 is not connected to a semiconductor device 100, the connection detection signal DET is a high level because the voltage Va is brought up to nearly power source voltage (VCC) via the output transistor 200. Therefore, the CPU 300 can recognize whether the load 200 is connected to the semiconductor device 100 by monitoring the detection signal DET.
Japanese Laid-open Patent Application No. 4-2209 is an example of prior art related to the first background art.
<Second Background Art>
FIG. 18 is a view showing a second conventional example of a load drive device and FIG. 19 is a timing chart showing an operation example of the load drive device shown in FIG. 18. During normal operation of the load drive device 100 (when a later-described overcurrent protection signal Sb is a low level), the input signal SA inputted to an input terminal IN is inputted to a pre-driver 102 via a Schmitt buffer 103 and a logic AND arithmetic unit 106. Here, when the input signal SA is a high level, a gate signal SB of the output transistor 101 is set at a high level, the output transistor 101 is switched on, and the output voltage VOUT that appears at the output terminal OUT is brought down to a low level (near ground potential (GND)). Conversely, when the input signal SA is a low level, the gate signal SB of the output transistor 101 is set at a low level, the output transistor 101 is switched off, and the output voltage VOUT that appears at the output terminal OUT is brought up to a high level (near power source potential (VCC)).
On the other hand, when the output current IOUT that flows to the load 200 reaches a predetermined threshold, the overcurrent protection circuit 104 detects that the output current IOUT is in an overcurrent state and sets the overcurrent detection signal SA from a low level to a high level. A mask time generation circuit 105 sets the overcurrent protection signal Sb from a low level to a high level when the overcurrent detection signal Sa has been kept at a high level over a predetermined mask time Tm. The logic AND arithmetic unit 106 outputs to the pre-driver 102 the logic AND signal of the input signal SA inputted to a non-inverted input terminal and the overcurrent protection signal Sb inputted to an inverted input terminal. Specifically, when the overcurrent protection signal Sb is a high level, the input signal (the output signal of the logic AND arithmetic unit 106) of the pre-driver 102 does not depend on the logic level of the input signal SA and is constantly a low level, the gate signal SB of the output transistor 101 is forcibly set to a low level, and the output transistor 101 is forcibly switched off.
Japanese Laid-open Patent Application No. 2006-229864 is an example of prior art related to the second background art.